新建一个IP

TB

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2024/05/17 19:48:41
// Design Name: 
// Module Name: tb_shift_ram
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//
module tb_shift_ram(
    );
reg clk,rst;   
initial begin
    clk=0;
    forever #4.545 clk=~clk;
end
initial begin
    rst=1;
    #9.09 rst=0;
end
reg [31:0] cnts;
always @ (posedge clk or posedge rst)
begin
	if(rst)
	begin
	cnts <= 32'd0;
	end
	
	else if(cnts <= 32'd100)
	begin
	cnts <=  cnts + 1'b1;
	end
	
	else
	begin
	cnts <=  cnts;
	end
end
wire [31:0] cnts_ram;
c_shift_ram_32_32 U_DELAY_ACC (
  .A(5'd7                                   ), // input wire [5 : 0] A
  .D(cnts             ), // input wire [31 : 0] D
  .CLK(clk                                  ), // input wire CLK
  .CE(1'b1                    ), // input wire CE
  .Q(cnts_ram     )  // output wire [31 : 0] Q
); 
endmodule

仿真结果

输入7，实际延迟为9个周期，多2个周期；