1. clock

module top_module ( );
    
    reg clk;
    initial
        begin
           clk = 1'b0;
        end
    
    always #5 clk = ~clk;
    dut t1(clk);
 
endmodule

2. testbench 1

module top_module ( output reg A, output reg B );//
    // generate input patterns here
    initial begin
		A = 1'b0;
        B = 1'b0;
        #10 A = ~A;
        #5  B = ~B;
        #5 A = ~A;
        #20 B = ~B;
    end
endmodule

3.Andgate 

module top_module();
   
    reg [1:0] in;
    reg out;
    
    initial
        begin
            in[0]= 1'b0;
            in[1] = 1'b0;     
            #10 in[0] = ~in[0];
            #10 in[0] = ~in[0];
            in[1] = ~in[1];
            #10 in[0] = ~in[0];
         end
    andgate t1(.in(in),.out(out));
endmodule

4.testbench 2 

module top_module();
    
    reg clk;
    reg in;
    reg [2:0] s;
    reg out;
    
    initial
        begin
           clk = 1'b0;
           in  = 1'b0;
            s = 3'd2;
        end
    
    always #5 clk = ~clk;
    
    initial
        begin
           #10	s = 3'd6;
           #10  in = ~in;
            	s = 3'd2;
            #10 in = ~in;
            	s = 3'd7;
            #10 in = ~in;
            	s = 3'd0;
            #30 in = ~in;
            	s = 3'd0;
  
        end
    
    q7 t1(
        .clk(clk),
        .in(in),
        .s(s),
        .out(out)
    );
    
    
endmodule

5.Flip-flop

module top_module ();
	
    reg clk;
    reg reset;
    reg t;
    reg q;
    
    initial
        begin
           clk = 1'b0;
           reset = 1'b0;
           t = 1'b0;
        end
    
    always #5 clk = ~clk;
    
    initial
        begin
           #6 reset = ~reset;
           #15 reset = ~reset;
        end
    
    always@(posedge clk)
        begin
            if(reset)
                t <= 1'b0;
            else
                t <= 1'b1;
        end
    
    tff t1(
        .clk(clk),
        .reset(reset),
        .t(t),
        .q(q)
    );
    
    
endmodule